lecture_EE1D1_lec9_sequential_modules_2025-10-21

📌 Overview

This lecture explores sequential logic timing and modules in digital systems. Key topics include flip-flop timing constraints, types of flip-flops (D, T, JK), registers, shift registers, counters (asynchronous/synchronous, up/down, BCD, ring, Johnson), and FSM implementation using counters. Emphasis on design steps for timing analysis, counter construction, and state transitions to ensure reliable operation up to max clock frequency.

Goal: Enable solving exercises on timing verification, flip-flop selection, counter design, and FSM-counter hybrids.

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🎯Learning Objectives

• Understand timing requirements for sequential circuits (setup/hold times, max frequency).
• Explain D, T, and JK flip-flops, including characteristic tables and conversions (e.g., JK to T).
• Interpret registers and shift registers for data storage/shifting.
• Design structured counters (synchronous/asynchronous, with enable/load/clear).
• Analyze BCD, ring, and Johnson counters for specific sequences.
• Implement FSMs using counters for state encoding and transitions.

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💡Key Concepts & Definitions

Sequential vs Combinational

• Sequential: State-dependent (uses memory elements like flip-flops); outputs depend on current state + inputs.
• Timing Constraints: Ensure stable operation; violations cause metastability or errors.
  • Setup Time (t_su): Min time D input stable before clock edge.
  • Hold Time (t_hold): Min time D input stable after clock edge.
  • Clock-to-Q (t_cQ): Delay from clock edge to Q output change.
  • Combinational Delay: t_comb,max (longest path), t_comb,min (shortest path).

Flip-Flops

• D Flip-Flop: Q(t+1) = D. Simple storage. Add preset (set Q=1) or clear (reset Q=0).
  • Characteristic:

D	Q(t+1)
0	0
1	1

• T Flip-Flop: Toggle on T=1, hold on T=0. Derived from D: D = T ⊕ Q.
  • Use: Counters (each stage toggles).
  • Characteristic:

T	Q(t+1)
0	Q(t)
1	¬Q(t)

• JK Flip-Flop: Versatile; J=set, K=reset, JK=1=toggle. Derived: Q(t+1) = J¬Q + ¬K Q.
  • Convert JK to T: Tie J=K=T.
  • Characteristic:

J	K	Q(t+1)
0	0	Q(t)
0	1	0
1	0	1
1	1	¬Q(t)

When to Use:

• D: General storage/registers.
• T: Simple counters (toggle stages).
• JK: Counters needing set/reset/toggle.
• Rare: If t_cQ < t_hold (uncommon), add delay buffers to min paths.

Registers & Shift Registers

• Register: n D-FFs with shared clock; stores n bits (parallel load via inputs I[3:0]).
• Shift Register: Serial in/out; shifts bits right/left on clock (e.g., divide-by-2 for right shift).
• Parallel-Access Shift Register: Mode select (S=0: shift; S=1: parallel load). Converts serial↔parallel.

Counters

• Asynchronous (Ripple): No global clock; each FF clocks from prior Q. Fast but skew-prone (drawback: propagation delay accumulates, limits freq).
• Synchronous: Global clock; all FF update parallel. Use AND gates for enable (e.g., T_i = Enable · Q_{i-1}…Q_0).
• Up/Down: Up increments; down uses ¬Q for toggle logic.
• With Enable/Clear/Load: AND enable to inputs; OR clear to ¬Q; MUX for load (Load=1 bypasses count logic).
• BCD Counter: Counts 0-9 (0000-1001); reset at 1010. Next state: If Q3Q2Q1Q0 > 1001, load 0000; else increment.
• Ring Counter: n-FF shift register circulating ‘1’ (one-hot codes). Init: Preset one FF. Sequence length n. Use: Sequencing (e.g., control signals).
• Johnson Counter: Ring variant; feedback ¬Q_n to D_0. Sequence length 2n (no invalid states). Init: Reset all. Use: Longer sequences with fewer FFs.
• FSM with Counter: Encode states as count values (e.g., S0=000). Transitions:
  • Hold: Load=Enable=0.
  • Next: Enable=1 (increment).
  • Jump: Load=1 (set D= target state).
  • Allowed: When states are consecutive (increment ok); else load. Rare: Overlap states cause glitches—use one-hot if needed.

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➗ Formulas

Timing Analysis

• Max Clock Period (T_min): T > t_cQ + t_comb,max + t_su
  → Max Freq (f_max) = 1 / (t_cQ + t_comb,max + t_su)
  Ex: t_cQ=1ns, t_comb,max=5.2ns, t_su=0.6ns → f_max = 1/6.8ns ≈ 147 MHz.

• Setup Slack: T - (t_cQ + t_comb,max + t_su) > 0 (per path).
  Negative slack → Increase T (lower freq) or optimize logic.

• Hold Check: t_cQ + t_comb,min ≥ t_hold
  Usually holds (t_cQ > t_hold); if not, add buffers to short paths.

Steps to Solve Timing Problem:

1. Identify critical path (longest t_comb,max via simulation/tools).
2. Calculate T_min from delays.
3. Verify hold: If violation, insert delay in min path.
4. If slack negative, pipeline or reduce logic depth.
5. Rare: Clock skew—align edges with buffers.

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✍️ Notes

Flip-Flop Timing Diagram

\usepackage{circuitikz}
\begin{circuitikz}
\draw (0,0) node[ffedge, edge label' = clock] (ff) {};
\draw (ff.Q) -- ++(1,0) node[right] {Q};
\draw (0,-1) -- (ff.D) node[left] {D};
\draw (ff.clk) -- ++(-0.5,0) -- ++(0,1) -- ++(0.5,0);
\node at (0.5,-0.5) {t_su};
\node at (0.5,-1.5) {t_hold};
\node at (1.5,0.5) {t_cQ};
\end{circuitikz}

• D stable during [t_su before, t_hold after] edge. Violation → undefined Q.

Designing Synchronous 4-Bit Up-Counter (T-FF)

Steps:

1. Choose FF type: T for toggle.
2. States: 0000 → 0001 → … → 1111 (overflow reset if needed).
3. For sync: T_0 = Enable; T_i = Enable · Q_{i-1} · … · Q_0 (AND chain detects all-lower=1).
4. Add Clear: Asynchronous reset all Q=0.
5. Verify timing: Critical path = AND chain delay + t_cQ + t_su.

Verilog Snippet (for sim):

module up_counter #(parameter N=4) (
    input clk, enable, clear,
    output [N-1:0] Q
);
    genvar i;
    generate
        for (i=0; i<N; i=i+1) begin : ff_gen
            t_ff tff (.clk(clk), .t(i==0 ? enable : &{Q[i-1:0], enable}), .clear(clear), .q(Q[i]));
        end
    endgenerate
endmodule

Example Question: Design 3-bit sync up-counter with enable. What is T_2 input?
Stepwise Solution:

1. States: Q2 Q1 Q0 from 000 to 111.
2. T_0 = Enable (toggle on enable).
3. T_1 = Enable · Q0 (toggle when Q0=1).
4. T_2 = Enable · Q1 · Q0 (toggle when Q1=Q0=1).
5. Allowed: Always (binary count). Rare: If mod-6, add reset logic at 110.

BCD Counter Design Steps

1. Define range: 0-9 per digit (0000-1001).
2. Next state: If current > 1001 (Q3=1, Q0-Q2 any) or =1010-1111, load 0000; else Q_next = Q +1 (XOR + carry).
3. Use D-FF: D_i = increment logic.
4. For multi-digit: Chain carries (e.g., 00-99).
5. Timing: Check carry path for t_comb,max.

Mermaid Diagram: BCD State Transition

stateDiagram-v2
    [*] --> 0000
    0000 --> 0001 : clk
    0001 --> 0002 : clk
    0002 --> 0003 : clk
    0003 --> 0004 : clk
    0004 --> 0005 : clk
    0005 --> 0006 : clk
    0006 --> 0007 : clk
    0007 --> 0008 : clk
    0008 --> 0009 : clk
    0009 --> 0000 : clk (reset)
    note right of 0009 : Detect 1010+ → load 0000

Example Question: For 4-bit BCD, next state of 1001 (9)?
Stepwise:

1. Current=1001 (9).
2. Increment: 1001 +1 = 1010 (10, invalid).
3. Detect invalid (Q3=1 & (Q2=0 | Q1=1 | Q0=1? Wait, standard: if >=1010, reset).
4. Load 0000.
5. Allowed: Decimal apps (displays). Not for binary (wastes states 1010-1111).

Ring vs Johnson Counter

• Ring (4-bit): Init 1000 → 0100 → 0010 → 0001 → 1000. Length 4. One-hot.
• Johnson (4-bit): Init 0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001 → 0000. Length 8. Mobius loop. Steps to Design Ring:

1. n D-FFs, serial in = Q_{n-1}.
2. Preset one FF=1.
3. Shift on clk.
   Rare: Lock-up if init wrong (all 0/1) → add decode reset.

Example Question: Johnson counter stuck? Why?
Stepwise:

1. Feedback ¬Q3 to D0.
2. If all 1: Shifts to 0111 (ok). All 0: Stays 0 (stuck).
3. Fix: Reset to 0000, but enable shift only after init.
4. Allowed: Cyclic sequences. Not for arithmetic count.

FSM with Counter Example (from slides)

States S0=000 to S7=111, input A.
Diagram:

stateDiagram-v2
    S3 --> S3 : A=1 (hold)
    S3 --> S7 : A=0 (load 111)
    S7 --> S4 : /0 (next?)
    note right of S3 : Q=011

Question: In S3 (011), possible next states?
Stepwise Solution:

1. Current Q2Q1Q0=011 (S3).
2. If A=1: Load=0, Enable=0 → hold S3.
3. If A=0: Load=1, D=111 → S7.
4. Possible: S3, S7. (Ans: b)
5. Allowed: Consecutive states use enable; jumps use load. Rare: If counter overflows, add mod logic.

Timing Ex: Given t_cQ=1ns, t_su=0.6ns, t_comb,max=5ns. f_max?

1. T_min = 1 + 5 + 0.6 = 6.6ns.
2. f_max = 1/6.6ns ≈ 152 MHz.
3. Check hold: Assume t_comb,min=0.5ns > t_hold - t_cQ (if t_hold=0.8ns, ok).

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🔗 Resources

• Presentation:
• Book: Fundamentals of Digital Logic with Verilog Design (Brown/Vranesic), Ch. 5.5-5.11.

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❓ Post lecture

1. Calculate setup slack for T=10ns, delays as above. (Ans: 10 - 6.6 = 3.4ns >0, ok.)
2. Convert JK to D: Set J=D, K=¬D.
3. Why async counters slower? (Ripple delay: n stages → T_max ~ n·t_cQ.)

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📖 Homework

• Exercises 3.9, 3.10 (Digital Design).
• Design 2-digit BCD counter: Sketch logic, verify seq 00→99→00.
• Simulate Johnson counter in tool (e.g., Logisim); fix init.