EE1D1

📚 Course: Digital Systems A

📌 Overview

High-level summary of the course. What are the main learning objectives?

studyguide

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lectures

File	Topic	Status	Created
lecture_EE1D1_lec1_2025-09-01	Binary adition and boolean operations	Pending	September 01, 2025
lecture_EE1D1_lec2_intro_2025-09-02	basic-logical system	Pending	September 02, 2025
lecture_EE1D1_lec3_systemVerilog_2025-09-08	SystemVerilog	Pending	September 08, 2025
lecture_EE1D1_lec4_logic_minimization_2025-09-09	logic minimization	Pending	September 09, 2025
lecture_EE1D1_lec5_combinational-and-floating-point_2025-09-15	combinational-modules implementation-technology floating-point-numbers	Pending	September 11, 2025
lecture_EE1D1_lec6_sequential_circuits_2025-10-07	sequential_circuits	Pending	October 07, 2025
lecture_EE1D1_lec7_FSM_2025-10-07	Finite State Machines	Processed	October 07, 2025
lecture_EE1D1_lec8_SystemVerilog-sequential-circuits_2025-10-13	SystemVerilog-sequential-circuits	Pending	October 13, 2025
lecture_EE1D1_lec9_sequential_modules_2025-10-21	sequential_modules	Pending	October 20, 2025

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🎯 Learning Objectives

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🧪 Labs

File	Status
lab_EE1D1_4_FPGA_counter_2025-10-16	-
lab_EE1D1_3_FSM_sequential_2025-10-15	-
lab_EE1D1_2_combinational-circuits_2025-09-25	Done
lab_EE1D1_1_system_verilog_2025-09-16	Done

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📄 Assignments

File	Status	Due Date

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✅ Exam Readiness Checklist

Topic / Skill	Know for Certain	I Think I Know	Need to Study

🔗 Resources & Links

• Syllabus:
• Professor Contact:
• Study Group Notes: Book:

📝 Study guide

study guide

📚 Course Overview

This course, Digital Systems A (EE1D1), provides the fundamental knowledge of digital systems. You’ll learn to design, simulate, build, and emulate both custom and standard digital circuits. Key hardware topics covered include:

• Overall design of computer systems
• Data representation in computers
• Boolean algebra & logic minimization
• Sequential circuits & Finite State Machines (FSMs)
• Standard modules (multiplexers, registers, etc.) You’ll also be introduced to SystemVerilog, a hardware description language, for practical lab sessions.

💡 Key Topics & Concepts

• Introduction to Digital Design: Representation, number systems
• Boolean Algebra: Foundations for digital logic
• Logic Minimization: Simplifying digital circuits
• Sequential Circuits and FSMs: Designing circuits with memory
• Standard Modules: Multiplexers, decoders, ROM, registers, counters
• Digital Implementation Technology: CMOS gates
• SystemVerilog: Structural, behavioral modeling, testbenches, simulation

✅ Learning Objectives

Upon successful completion, you should be able to:

• Explain how digital systems work and are constructed.
• Describe digital circuits using Boolean algebra and simplify them.
• Design and Analyze custom and standard combinatorial and sequential circuits.
• Implement Finite-State Machines.
• Describe and Analyze digital circuits in CMOS technology.
• Create, Simulate, and Emulate structural and simple behavioral SystemVerilog descriptions.

👩‍🏫 Teaching Method & Contact

• Method: Lectures, seminars, lab sessions
• Contact Hours/Week: 6 hours (Lectures/Seminars/Labs)

📊 Assessment Breakdown

The final grade is determined by a combination of partial exams (T) and online tests (R).

1. Calculate Exam Grade (T):

• T = (Partial Exam 1 + Partial Exam 2) / 2

2. Calculate Online Test Average (R):

• R = (Week 4 Test + Week 8 Test) / 2
• Note: A missed test counts as a 0.

3. Calculate Final Grade (C):

• Formula: C = T + R * (10 - T) / 100

Important Conditions:

• Labs: All course lab assignments must be successfully completed.
• Rounding: The final grade C is calculated with one decimal place and rounded up to the nearest half point.
• Resit: The resit covers both partial exams. The R score is only valid for the current academic year.

• Partial Exams: Two written partial exams, averaged for Exam Grade T.
• Online Tests: Tests in Week 4 and Week 8. Average result (0-10) is R (non-made test results in a 0).
• Final Grade C Calculation: C = T + R * (10-T) / 100. This is calculated with one decimal accuracy and rounded up to half.
• Course Lab Assignments: Must be successfully completed for the final mark to be valid.
• Resit: Includes contents of both partial exams. R (online test result) is valid only for the current year’s exams/resit. Partial exam results are not transferable to the next academic year.

📚 Literature and Course Materials

• Textbook: Digital Design and Computer Architecture, RISC-V Edition (July 12, 2021) by Sarah Harris, David Harris.
• Lecture Slides
• Course Lab Manual