lecture_EE1D1_lec6_sequential_circuits_2025-10-07

📌 Overview

Sequential circuits are a type of logic circuit whose output depends not only on the present value of its input signals but also on the sequence of past inputs. This is in contrast to combinational logic, whose output is a function of only the present input. Sequential circuits have memory elements to store the state of the circuit.

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🎯Learning Objectives

• Explain how sequential networks work
• Interpret circuits with memory elements (i.e., latches, flip-flops)
• Explain Finite State Machines
• Design Finite State Machines (Moore and Mealy type)

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💡Key Concepts & Definitions

• Sequential Circuit: A digital logic circuit in which the output depends on the present input as well as the past sequence of inputs. It uses memory elements to store information about past events.
• Latch: A level-sensitive memory device that changes its output as long as the clock signal is active (e.g., high). It is transparent.
• Flip-Flop: An edge-triggered memory device that changes its output only at the rising or falling edge of the clock signal.
• Finite State Machine (FSM): A model of computation used to design sequential logic circuits. It consists of a finite number of states, transitions between those states, and outputs.
• Moore Machine: An FSM where the outputs depend only on the current state.
• Mealy Machine: An FSM where the outputs depend on both the current state and the current inputs.

➗ Formulas

There are no specific formulas for this lecture. The focus is on circuit diagrams and state tables.

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✍️ Notes

Sequential Networks

Sequential networks are essential for building digital systems that require memory. Unlike combinational circuits, their outputs are a function of both current and past inputs.

Bistable Circuit

The fundamental building block of memory elements is the bistable circuit, which has two stable states. It can be constructed using two cross-coupled inverters.

graph TD
    A[Inverter 1] --> B[Inverter 2];
    B --> A;

Latches

SR Latch

An SR latch is a simple memory element with two inputs: S (Set) and R (Reset).

• Set (S=1, R=0): Sets the output Q to 1.
• Reset (S=0, R=1): Resets the output Q to 0.
• Memory (S=0, R=0): Holds the previous state.
• Invalid (S=1, R=1): This state is forbidden as it leads to an undefined output.

Here is the circuit diagram for a NOR SR Latch:

D Latch

A D latch has a data input (D) and a clock input (CLK). It avoids the invalid state of the SR latch.

• When CLK is high, the output Q follows the input D (transparent).
• When CLK is low, the output Q holds its previous value.

Flip-Flops

D Flip-Flop

A D flip-flop is an edge-triggered device. The output Q only changes on the rising or falling edge of the clock.

• Positive Edge-Triggered: Q is updated with the value of D on the rising edge of the clock.
• Negative Edge-Triggered: Q is updated with the value of D on the falling edge of the clock.

Here is a comparison of a D Latch and a D Flip-Flop:

Feature	D Latch	D Flip-Flop
Triggering	Level-sensitive	Edge-triggered
Transparency	Transparent when CLK is active	Never transparent
Use Case	Simple memory applications	Synchronous systems

Finite State Machines (FSM)

An FSM is a powerful tool for designing synchronous sequential circuits. It consists of a state register and combinational logic.

FSM Design Steps

1. State Diagram: A graphical representation of the FSM.
2. State Table: A tabular representation of the state diagram.
3. State Assignment: Assign binary codes to the states.
4. Flip-Flop Choice and Next-State/Output Expressions: Choose a flip-flop type and derive the logic expressions for the next state and outputs.
5. Implementation: Implement the logic using gates.

Example: Sequence Detector (Moore Style)

Problem: Design an FSM that outputs z=1 when the input w has been 1 for two consecutive clock cycles.

State Diagram:

graph TD
    A((A/0)) -- w=0 --> A;
    A -- w=1 --> B((B/0));
    B -- w=0 --> A;
    B -- w=1 --> C((C/1));
    C -- w=0 --> A;
    C -- w=1 --> C;```

**State Table**:

| Present State | Next State (w=0) | Next State (w=1) | Output (z) |
| :--- | :--- | :--- | :--- |
| A | A | B | 0 |
| B | A | C | 0 |
| C | A | C | 1 |

#### Example: Sequence Detector (Mealy Style)

**State Diagram**:

```mermaid
graph TD
    A((A)) -- w=0/0 --> A;
    A -- w=1/0 --> B((B));
    B -- w=0/0 --> A;
    B -- w=1/1 --> B;

State Table:

Present State	Next State (w=0)	Next State (w=1)	Output (z, w=0)	Output (z, w=1)
A	A	B	0	0
B	A	B	0	1

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🔗 Resources

• Presentation:

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❓ Post lecture

• What is the main difference between a latch and a flip-flop?
• Why is the S=1, R=1 state invalid in an SR latch?
• When would you choose a Moore machine over a Mealy machine?

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📖 Homework

• Reading Material: “Digital Design” Sections 3.1 – 3.3 (not 3.2.7)
• Assignments: Gated Practice Assignment Lecture 6